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this is information on a product in full production. march 2012 doc id 019007 rev 3 1/13 13 STFI20NK50Z n-channel 500 v, 0.23 , 17 a zener-protected supermesh? power mosfet in i2pakfp package datasheet ? production data features fully insulated and low profile package with increased creepage path from pin to heatsink plate extremely high dv/dt capability 100% avalanche tested gate charge minimized applications switching applications description this device is an n-channel zener-protected power mosfet developed using stmicroelectronics' supermesh? technology, achieved through optimization of st's well- established strip-based powermesh? layout. in addition to a significant reduction in on- resistance, this device is designed to ensure a high level of dv/dt capability for the most demanding applications. figure 1. internal schematic diagram type v dss r ds(on) max i d p tot STFI20NK50Z 500 v < 0.27 17 a 40 w i 2 pakfp 1 2 3 (to-281) d(2) g(1) s(3) am01476v1 table 1. device summary order codes marking package packaging STFI20NK50Z 20nk50z i 2 pakfp (to-281) tube www.st.com
contents STFI20NK50Z 2/13 doc id 019007 rev 3 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 STFI20NK50Z electrical ratings doc id 019007 rev 3 3/13 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage 500 v v gs gate-source voltage 30 v i d drain current (continuous) at t c = 25 c 17 (1) 1. limited by maximum junction temperature. a i d drain current (continuous) at t c = 100 c 10.71 (1) a i dm (2) 2. pulse width limited by safe operating area. drain current (pulsed) 68 a p tot total dissipation at t c = 25 c 40 w esd gate-source human body model (r=1,5 k , c=100 pf) 6kv v iso insulation withstand voltage (rms) from all three leads to external heat sink (t = 1 s; t c = 25 c) 2500 v dv/dt (3) 3. i sd < 17 a, di/dt < 200 a/s, v dd =80% v (br)dss peak diode recovery voltage slope 4.5 v/ns t stg storage temperature -55 to 150 c t j max operating junction temperature 150 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 3.1 c/w r thj-amb thermal resistance junction-ambient max 62.5 c/w table 4. avalanche characteristics symbol parameter value unit i ar (1) 1. limited by maximum junction temperature. repetitive or non repetitive avalanche current 17 a e as single pulse avalanche energy (starting t j =25 c, i d =i ar , v dd =50 v) 850 mj electrical characteristics STFI20NK50Z 4/13 doc id 019007 rev 3 2 electrical characteristics (t case = 25 c unless otherwise specified) table 5. on/off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d =1 ma 500 v i dss zero gate voltage drain current (v gs = 0) v ds = 500 v v ds = 500 v, t c = 125 c 1 50 a a i gss gate-body leakage current (v ds = 0) v gs = 20 v 10 a v gs(th) gate threshold voltage v ds = v gs , i d = 100 a 3 3.75 4.5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 8.5 a 0.23 0.27 table 6. dynamic symbol parameter test conditions min. typ. max. unit g fs (1) 1. pulsed: pulse duration=300s, duty cycle 1.5% forward transconductance v ds = 15 v, i d = 8.5 a - 13 s c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 25 v, f = 1 mhz, v gs = 0 - 2600 328 72 pf pf pf c oss eq. (2) 2. c oss eq. is defined as a constant equivalent capac itance giving the same charging time as c oss when v ds increases from 0 to 80% v dss . equivalent output capacitance v ds =0, v ds = 0 to 640 v - 187 pf t d(on) t r t d(off) t f tu r n - o n d e l ay t i m e rise time turn-off delay time fall time v dd = 250 v, i d = 8.5 a, r g = 4.7 , v gs = 10 v (see figure 15 ) - 28 20 70 15 ns ns ns ns q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 400 v, i d = 17 a, v gs = 10 v (see figure 16 ) - 85 15.5 42 119 nc nc nc STFI20NK50Z electrical characteristics doc id 019007 rev 3 5/13 the built-in back-to-back zener diodes have specifically been designed to enhance not only the device?s esd capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. in this respect the zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device?s integrity. these integrated zener diodes thus avoid the usage of external components. table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm (1) 1. pulsed: pulse duration=300s, duty cycle 1.5% source-drain current source-drain current (pulsed) - 17 68 a a v sd (2) 2. pulse width limited by safe operating area. forward on voltage i sd = 17 a, v gs = 0 - 1.6 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 17 a, di/dt = 100 a/s v r = 100 v (see figure 17 ) - 355 3.90 22 ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 17 a, di/dt = 100 a/s v r = 100 v, tj = 150 c (see figure 17 ) - 440 5.72 26 ns c a table 8. gate-source zener diode symbol parameter test conditions min. typ. max. unit v (br)gso gate-source breakdown voltage (i d = 0) i gs = 1ma 30 - v electrical characteristics STFI20NK50Z 6/13 doc id 019007 rev 3 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. transconductance figure 7. static drain-source on resistance STFI20NK50Z electrical characteristics doc id 019007 rev 3 7/13 figure 8. gate charge vs gate-source voltage figure 9. capacitance variations figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on resistance vs temperature figure 12. maximum avalanche energy vs temperature figure 13. normalized b vdss vs temperature - ; a ` a d _ h 9 e f z f < z 5 h 6 e / h 9 e ; 6 / # " " g 3 a - ; a d 6 e a ` ` a d _ f < z 5 h 9 e / # " h ; 6 / * ' 3 a - ; 7 s e _ < |